Hierarchical Design Hardware Constraints EE348/CS338


 

Xilinx  Foundation  Tutorial

Volker Strumpen
Depts. of Electrical Engineering and Computer Science
Yale University
 

    This is a brief tutorial for the Xilinx Foundation Software.  It targets first-time users who want to get started with the Foundation Software to synthesize a digital design.  During the course of the tutorial, all steps of the synthesis process are covered using a half-adder as running example.  We start with the input of the circuit in the schematic editor, simulate the timing behavior of the circuit, compile it for an XC4010XL FPGA, and test the design on an XS40/XStend prototyping board.

    This tutorial is for the Foundation Series Software, Version 1.4, running on the lab machines.  In particular, screen dumps have been generated from that version.  Several details in the Xilinx Student Edition deviate slightly from this description.  I explain the differences in the text.

    The tutorial contains the following steps:

  1. Project Manager: How to Create a New Project
  2. Schematic Editor: How to Create a Schematic
  3. Simulator: How to Simululate a Circuit
  4. Implementation: How to Compile into Hardware
  5. Verification: How to Test the Design on an XS40 Board

    The following sections provide additional information:

        Hints and Quirks
        Exercises
        References
 
 

    In the Start menu of Windows NT, goto Programs, goto Xilinx Foundation Series, and click on Xilinx Foundation Project Manager to start the Project Manager.  Pull down the File menu and click on New Project. A new window entitled ``New Project'' appears.  The state of affairs is shown in Figure 1 below.
 
 
Project Manager with New Project window
 
Figure 1:  Project Manager window with popup window for New Project
 

In the Name field of the New Project window type ``adder'' and click OK.  Now, a new project hierarchy is generated and is displayed in the left portion of the Project Manager window in Figure 2.  It contains the file ``ADDER.UCF'', and directories ``ADDER'', ``SIMPRIMS'' and ``XC4000E''.  Note that a project is no more than a collection of files in a directory hierarchy.  You can figure out where your files are located, and browse through that hierarchy by selecting the Open Project item in the File menu of the Project Manager.
 
 

Project Manager with new adder hierarchy
 
Figure 2:  Project Manager window with new adder project.  Note: In the Xilinx Student Edition, the ``Implement'' button is named ``XACT Step.''
 

Note that the action of having generated a new project is logged in the bottom part of the Project Manager window.  We are now ready to create a schematic for our half-adder.
 
 

    In the right part of the Project Manager, cf. Figure 2, click on the button entitled Schematic Editor.  (Another button with the same effect can be found in the toolbar; it's the sixth button from the left marked with an AND-gate icon.)  Having activated the Schematic Editor, a new window appears entitled ``Schematic Capture''.  At the same time, a new file with name ``ADDER1.SCH'' is inserted in the project hierarchy shown in the Project Manager.  Later in the design process, clicking on that name in the Project Manager will automatically start up the Schematic Editor.  The design of our half-adder is shown in the Schematic Editor window in Figure 3.
 
 
Adder schematic in Schematic Editor
 
 
Figure 3:  Schematic Editor window with half-adder schematic
 

    A schematic is generated by inserting gates and input/output pads.  The inputs and outputs of the gates and pads are connected by means of wires.  Standard symbols such as the inverter ``INV'', the AND-gate ``AND2'', and the OR-gate ``OR2'' can be found in the ``Symbol Toolbox''.  The Symbol Toolbox is opened by a click on the button with the gate symbol in the vertical toolbar on the left border of the Schematic Editor (buttom eight from the bottom), or by pulling down the Mode menu and selecting Symbols.  A screen dump of the Symbol Toolbox is shown in Figure 4 below.
 
 

Symbol Toolbox
 
Figure 4:  Symbol Toolbox window
 

    According to the naming convention in the symbol toolbox, gates are listed by a (sort of) descriptive name, such as ``AND'' or ``OR''.  Most names end with a number, often describing the number of inputs into the gate.  For example, an AND-gate with two inputs and one output is named ``AND2''.  Analogously, the name for an OR-gate with two inputs and one output is ``OR2''.  Gates with a single input don't have the number of inputs appended to the name, as for example for the inverter, which is simply named ``INV''.  You may insert a gate in the drawing area of the Schematic Editor by left-clicking on the name in the Symbol Toolbox, and by moving the cursor into the drawing area.  The symbol for the gate appears attached to the cursor.  Moving the mouse drags the gate across the drawing area.  Left-clicking the mouse again in the drawing area causes the gate symbol to be inserted at the current mouse position.  This process can be repeated until all gates are positioned approximately where they are intended to end up.  Figure 5 shows the gates dropped for the half-adder.
 
 

Adder gates inserted
 
Figure 5:  Schematic Editor window with gates for half-adder
 

    Close the Symbol Toolbox by left-clicking on the Symbol Toolbox bottom in the vertical toolbar or by double-clicking on the top-left corner of the Symbol Toolbox window.  We are now back in editing (select and drag) mode, and can move the gates around by selecting them with a left-click and dragging them across the drawing area.  Releasing the left mouse button drops the gate in the current position.  It is often convenient to use a grid for orientation.  If not enabled in your editor, pull down the View menu and click on Grid.  Snapping all movements to the grid simplifies aligning the symbols even further. A Snap to Grid option can be found in the View menu of the Schematic Editor as well.
 

    The next step is to add input/output pads to our collection of gates.  Click on the terminal button (third from bottom of the vertical button bar in the Schematic Capture window).  A dialog window entitled ``I/O Terminal'' appears.  This situation is shown in Figure 6.  In the Name field type the terminal name ``A'', select Terminal Type ``INPUT'', and click OK.  An input pad is now attached to the cursor.  As with gates, drag the terminal to its intended position in the drawing area and drop it with a single left-click.  Add another input pad named B, and two output pads named SUM and CARRY to the schematic.
 

Insert I/O Terminals
 
Figure 6:  Schematic Editor window with I/O Terminal window
 
 
    The next step is to wire up the circuit.  Click on the wire button (seventh from the bottom of the vertical button bar in the Schematic Capture window) to enter the ``Draw Wires'' mode.  Alternatively, click on the Draw Wires item in the Mode menu.  Then, as shown in Figure 7, move the cursor to the wire hanging off the input pad (position A), and left-click.  Move the cursor to the input wire of the inverter (position B), and left-click again. The blue wire shown in Figure 7 appears.  Insert all connections shown in Figure 3.  You can leave the ``Draw Wires'' mode by right-clicking the mouse.
 
 
Insert Wires
 
Figure 7:  Connect the input pad and the inverter by selecting the ``Draw Wires'' mode, left-click at position A, and left-click at position B again.
 
 
      Start the simulator by clicking on the SIM Funct button in the Project Manager window, cf. Figure 2.  The Waveform Viewer window of the Logic Simulator, shown in Figure 8, appears on the screen.
 
Logic Simulator
 
Figure 8:  Waveform Viewer window of the Logic Simulator.  Note that the layout of the Logic Simulator window in the Xilinx Student Edition is different.  It provides the buttons shown in the toolbar in a separate window.
 

 Three steps are required to produce a functional simulation of our half-adder circuit:

  1. Select the signals whose logic values we want to examine.
  2. Define input signals to stimulate the circuit.
  3. Run the simulation to produce the timing waveforms for the chosen input signals.
We examine each of the three steps in turn.
      Signals are selected by selecting the Add Signals item in the Signal pulldown-menu of the Logic Simulator window, cf. Figure 8.  The Component Selection window appears.
 
 
Figure 9:  Selecting signals for functional simulation
 

    Click on signal ``A'' in the Signals Selection portion of the window to select signal A, and add it to the waveform viewer by clicking
the Add button in the lower left corner of the Component Selection window.  Repeat the signal selection for signals ``B'', ``CARRY'', and ``SUM''.  Finally, return to the waveform viewer by clicking button Close.  The inputs and outputs are now displayed in the waveform viewer, cf. Figure 10.
 
 
 
 

    Input signals, so-called stimulators, are defined by selecting the Add Stimulators item in the Signal pulldown-menu.  The Stimulator Selection window appears as shown in Figure 10.
 
 
Figure 10:  Specifying input signals in the Stimulator Selection window
 

    The simplest way of adding a set of signals that generates all possible combinations of truth values is the 16-bit binary counter labeled Bc, which is represented by the row of 16 yellow LEDs in the Stimulator Selection window.  We can apply the sequence of truth values 00, 01, 10, and 11 to the inputs A and B of the half-adder circuit by assigning a Bc counter signal to the circuit inputs.  Click on signale name A of input A in the Waveform Viewer window, and subsequently click on the rightmost yellow LED of the Bc counter.  As a result, the LSB of the counter denoted B0 is assigned to input A.  Assign counter signal B1 to input B, and click on Close to leave the Simulator Selection window.
 
 
 
 

    The simulator is now ready to run a functional simulation of the half-adder circuit.  We have to choose several timing parameters, however,  to obtain a reasonable graphical representation of the timing waveform.

    Firstly, choose the clock period of the binary counter. Select the Preferences item in the Options pull-down menu of the Waveform Viewer window, cf. Figure 8.  The Preferences window, shown in Figure 11, appears.  In the Clocks section, select 100ns for the B0 period.  Click the OK button to leave the Preferences window.

 

 
Figure 11:  Choose clock period of input signal
 

    Secondly, choose the step sizes for the simulation. There are two different step sizes to proceed with the simulation.  Select the Simulation Step item in the Options pull-down menu of the Waveform Viewer.   The Step window, shown in Figure 12, appears.  Select ``100ns'' for the Short Step and ``500ns'' for the Long Step.  Click on the Set Step button to save the selection, and on Close to leave the Step window.
 

 
Figure 12:  Select time steps for simulation
 

    Thirdly, select the timing resolution of the Waveform Viewer by clicking on the zoom buttons right above the list of signals in the Waveform Viewer window until ``10ns/div'' appears.
 
    Finally, the timing simulation can be performed by clicking one of the buttons ``short step'' (button with short foot step symbol to the right of the ON button) or ``long step'' (button with long foot step symbol to the left of the STOP button) repeatedly.  Figure 13 shows the waveforms after executing one short step and two long steps.

 

 
Figure 13:  Waveforms due to functional simulation of half-adder circuit
 
 
      Before the half-adder design can be compiled into hardware, two more details need to be fixed up:
  1. Input and output buffers must be added to the terminals.
  2. Specifying the I/O Pin connections.
      Signals that cross the chip boundary via the FPGA's I/O pins must be buffered.  The Symbol Toolbox (Figure 4) contains so-called ``IBUFs'' and ``OBUFs''.  IBUFs must be inserted between all input pads and logic gates on the chip boundary and, analogously, OBUFs must be connected to output pads.  Figure 14 shows the modified half-adder circuit.

 

 
Figure 14:  Modified half-adder circuit with input and output buffers

 
    An input buffer can be added by loading the Symbol Toolbox, and dragging an IBUF symbol next to the wire where it shall be inserted.  Then, connect the input and output of the IBUF to that wire by means of new wires.  Select the wire segment (right-click to leave the ``Draw Wires'' mode and return into the ``Select and Drag'' mode) that bypasses the IBUF and remove it (click the scissors button).  Finally, drag the IBUF and its connecting wires around until they are in their intended position and shape.
 
 
 

    The pin assignment within the FPGA can be specified by means of a ``User Constraint File'' (UCF).  A template of such a file has been generated already when the project was opened originally.  In the Project Manager window, click on the file name ``ADDER.UCF'' (Figure 2) to open the UCF file in a new editor window.  Go to the end of the file and add the following constraints:     This will assign input A to pin 44 of the FPGA, input B to pin 45, output SUM to pin 59 and output CARRY to pin 3.  Take a look at the hardware constraints to find out how these pins are connected with the outside world.

    Don't forget to save the changes to the UCF file (Ctrl-S will do the job).
 
 
 

    We are now ready to implement the half-adder design, i.e. compile the FPGA configuration.  In the Project Manager, click the Implement button (or the XACT step button in the Xilinx Student Edition).  The Design Manager window, shown in Figure 15, appears.
 
 
 Design Manager
 
Figure 15:  The Design Manager window with an empty directory for the half-adder circuit
 

    Click the Implement item in the Design pulldown-menu of the Design Manager, and the Implement window appears on the screen, shown in Figure 16.
 

Design Manager's Implement Window
 
Figure 16:  The Implement window of the Design Manager
 

    Click on the Select button of the Implement window to select the FPGA type for which the design shall be implemented.  The Part Selector window appears, shown in Figure 17.
 

Design Manager's Part Selector window
 
Figure 17:  The Part Selector of the Implement window is used to specify the target device
 

    In the Part Selector window select the FPGA family ``XC4000XL'' and the device ``XC4010XL'', and click the OK button.  To tell the design manager where to find the UCF file, click on the Options button in the Implement window.  The Options window, shown in Figure 18, appears.
 

Design Manager's Options window
 
Figure 18:  The Options window of the Implement window
 
 

    In the Control Files section add the path to your file adder.ucf in the User Constraints dialog box.  Click OK to leave the Options window.

    Now, everything is set up to run the hardware implementation by clicking the Run button of the Implement window.  The Flow Engine window, shown in Figure 19, appears.
 

Design Manager's Flow Engine window
 
Figure 19:  The Flow Engine window reports the progress during the implementation
 

    The Flow Engine window shows the progress of the implementation.  In the screendump in Figure 19, the Configure step is running whereas the translation, mapping, and place&route steps are completed already.  Once the implementation procedure terminates successfully, a bitstream has been created and has been written into a file named ``adder.bit''.  This bitstream contains the configuration information for the XC4010XL FPGA.  We are now ready to check the completed half-adder design on the XS40 board.
 

 

    The half-adder design can be downloaded and tested with the XSTOOLS programs xsload and xsport.  To download the bitstream into the FPGA and, i.e. to configure the hardware, open a shell, enter the directory which contains the file ``adder.bit'', and execute the command:     Now, the hardware is configured with the half-adder design and we can apply bitstrings to its input pads to test the design.  The program xsport is used to that end.  We supply xsport with a bitstring  B1B0 as parameter.  Up to 8 bits can be applied to the input pads of the FPGA with each execution of xsport.  The mapping of the position of the parameter bits Bi and the pins of the FPGA is defined by the hardware constraints.

    Figure 20 shows a sample session in a Cygnus shell.  First, the FPGA is configured by running xsload.  Then, all possible combinations of truth values are applied to the input pads, using xsport.
 

 
Figure 20:  Sample session to download and test the half-adder circuit
 
      Verify that the lightning of the LED's corresponds to the input signals applied by the xsport command.

 
 

    Each window of the Foundation Software contains a Help button which provides online help when clicking on it.  A tutorial and other useful material is in the Online Books.  These are accessible from the Start menu in Windows NT.  Select Programs, then Xilinx Foundation Series, and finally Online Books.
 
    There are still some quirks in the Foundation software you may want to be aware of.  I list those of them that may cause trouble according to the steps of this tutorial.
 
 

  1. Modify the UCF file to attach the outputs SUM and CARRY to segments S0 and S6 of the seven-segment LED of the XS40 board (cf. hardware constraints), respectively. Explain the difference w.r.t. the tutorial's implementation.

  2. Modify the UCF file such that the SUM and CARRY outputs are attached to the diodes D7 and D8 of the XStend board (cf. hardware constraints), respectively.

  3. Modify the half-adder circuit such that the SUM and CARRY outputs are attached to the LEDs D7 and D8 of the XStend board (cf. hardware constraints), respectively, and the LEDs are lit when the outputs have a positive logic value of 1. Don't increase the critical path length of the circuit.

    Hint:  Use the generalized De Morgan's theorem: F'(X1, X2, ..., Xn) = FD(X1', X2', ..., Xn').


  4. Timing behavior.  Rather than performing a ``functional'' simulation of the half-adder, as described in Section 3, we might be interested in a more accurate timing behavior of the half-adder circuit.  In the selector field of the Waveform Viewer (just beneath the Device and Options pulldown menus), select Timing rather than Functional.

    Set the stimulator frequency of bit B0 of the binary counter to 1GHz.  Reset the simulator by pushing the red ON button, and perform the simulation for a long step size of 20ns.  Use a resolution of 500ps/div to view the resulting waveform.  What can you say about the resulting waveforms.

    Repeat the timing simulations for 100MHz, 10MHz and 1MHz.  Which conclusions can you draw from the timing simulations.


  5. Design, implement, and verify a decimal to seven-segment LED converter for the LED on the XS40 board.


  6. Design, implement, and verify a hexadecimal to seven-segment LED converter for one of the seven-segment LEDs on the XStend board. Use the radix point to distinguish letters from decimals digits where necessary.

 

  1. Dave Van den Bout, The Practical Xilinx Designer Lab Book, Prentice Hall, Upper Saddle River, 1998.

    2. This book comes with the Xilinx Student Edition, and provides plenty of useful hints about working efficiently with the Foundation Software.

Last  updated: $Date: 1998/11/01 18:18:43 $ by $Author: strumpen $
Copyright © 1998 Volker Strumpen
$Id: foundation.html,v 1.12 1998/11/01 18:18:43 strumpen Exp $